1. Field of the Invention
The present invention relates to integrated circuits, more particularly, to a semiconductor cell that avoids using power strips in order to reduce height of each semiconductor cell, thereby increasing integration of semiconductor circuits (i.e., integrated circuits) using semiconductor cells.
2. Description of the Prior Art
Semiconductor circuits (i.e., integrated circuits) are one of the most important hardware bases in the modern information society. A key design point of the semiconductor industry is to increase integration of integrated circuits, and therefore to use the area of integrated circuits more efficiently.
Generally speaking, integrated circuits having complex functions are made up of many circuit cells, each with basic functions. For example, cells of different kinds of logic gates, such as AND gates, OR gates, and inventors, cells of flip-flops, adders, and counters are always used to realize complex integral functions of digital integrated circuits. When designing an integrated circuit having specific functions, basic circuit cells that can realize the specific functions of the integrated circuit must be selected first. Next, with the basic cells already having been selected, designers draw out a layout design of the integrated circuit. Eventually, real semiconductor circuits (i.e., integrated circuits) are manufactured according to the layout design. As a person skilled in the art is familiar with, a semiconductor circuit is made up of many semiconductor layers with different characteristics. By designing different layouts on different semiconductor layers, connections between transistors are realized, and therefore each cell and the whole integrated circuit are formed.
For the convenience of integrated circuit design, designers always establish a library including frequently used cells and their corresponding layout designs. When designing an integrated circuit, designers determine which cells are going to be used, then arrange corresponding layout designs of these cells selected from the library to determine a layout design of the integrated circuit as a whole. Real integrated circuits can then be manufactured according to the layout design of the integrated circuit.
FIG. 1 is a diagram illustrating how layout designs of cells in a library are used in a conventional manner to realize an integrated circuit. In the conventional manner, a library 10 includes layout designs of a plurality of cells P(1), P(2), . . . , P(m), . . . , P(M). In the layout design of each cell, there are active region layout(s) df, such as layout location of doping well(s) and diffusion region(s), polycrystalline silicon layout(s) pl, first metal layer layout mt1, and contact layout(s) ct, etc. With different active regions and polycrystalline silicon layouts, basic semiconductor structures, such as the source, drain, and gate of a MOS, of transistors are formed. Each metal layer connects different transistors; contact layouts connect layouts of different layers. Some contact/via layouts, on the other hand, form signal input/output ends of each cell, i.e. they are signal layouts of each cell. The layout designs of different semiconductor layers constitute transistors of each cell, and the basic function of each cell is then realized.
Please note that in the prior art, each cell comprises power strips formed by metal layer layouts, for example, the above-mentioned first metal layer layout. As a person skilled in the art is familiar with, transistors of each cell must connect to appropriate DC power, such as a DC supply voltage VDD or ground voltage (for example Vss). In the prior art scheme, for connecting each cell to DC power, traverse power strip layouts pw1 and pw2 are set in each cell. Basically, as is shown in FIG. 1, two power strip layouts are set on two opposite ends of each cell, and the power strip layouts cross each cell, connecting two different sides of each cell. With the cells being arranged adjacently, power layouts of each cell are interconnected. Hence, all the cells can receive required DC power.
Please now consider an example. When designing an integrated circuit 12, if it is required that the integrated circuit 12 includes a cell P(m) and a cell P(M), designers can find the layout designs of the cells P(m) and P(M) from the library 10, arrange the layout designs in the layout of the integrated circuit 12, and connect power strips of the cells P(m) and P(M). Next, a routing procedure is performed to connect input/output signal conducts/vias of each cell. The function of the whole integrated circuit is then realized through the interconnected cells. For example, in FIG. 1, the routing procedure includes realizing a routing layout rt0 on the first metal layer to connect certain contacts of the cell P(m) with certain contacts of the cell P(M). Signal layouts of the two cells are then interconnected, signals can pass between the two cells, and the two cells can act as a whole to realize the functions of the integrate circuit 12. After the routing layout is realized, the routing procedure comes to an end, and layout design of the whole integrated circuit 12 is also finished. A semiconductor manufacturing process is then performed to produce real semiconductor integrated circuits.
The above-mentioned prior art has some drawbacks. In the layout design of each cell, there are power strips pw1 and pw2. The original intention of using these power strips is to relieve the designer from designing a special power layout, since power strips easily connect with each other to form a power layout of the whole integrated circuit. However, this kind of power strip layout design occupies a great amount of area and increases height of each cell. In other words, distance between layouts of two power strips of FIG. 1 cannot be reduced. With un-reducible cell height, the area of each cell also become un-reducible, hence, the integration of semiconductor circuit (i.e., the integrated circuit) cannot be increased efficiently.